Packaging an integrated circuit (IC) involves sealing the IC in a package suitable for installation in end products and enabling communication between the IC and devices outside of the package. Conventionally, communication in a packaged IC includes either wire bonds or through silicon vias.
A wire bond may be copper, gold, or another conductive material and is coupled to a contact pad on each end. Wire bond interconnects have a low interconnect density resulting from the large size of the contact pad required. The contact pads may be, for example, hundreds of square microns in area, which consumes a large quantity of the IC area. Additionally, during IC packaging a wire bond is enclosed in a bond shell to protect the wire bonds during later assembly. The bond shell further enlarges the size of the packaged IC. However, wire bonds are conventionally less costly to manufacture than through silicon vias.
Through silicon vias are holes through a silicon (or other material) substrate or die. The through silicon vias are filled with a conducting material and function as an interconnect from one side of the substrate or die to another side of the substrate or die. Although conventionally more costly to manufacture than wire bonds, through silicon vias may be manufactured in smaller sizes and higher densities than wire bonds. For example, a through silicon via may be only tens of microns in diameter.
Conventionally, either through silicon vias or wire bonds function as interconnects in a packaged IC. However, stacked ICs present additional challenges for packaging ICs. For example, when a second die is stacked on a first die, both dies must communicate to external devices through the packaging interconnect. The resulting number of interconnects between the first die and a packaging substrate is difficult to manage. For example, a stacked IC may have twice the number of packaging interconnects than in a conventional IC.
Thus, there exists a need for balancing the benefits and costs of wire bonds and through silicon vias in stacked ICs.